Generally, semiconductor devices include a plurality of circuits which form an integrated circuit (IC) fabricated on a semiconductor substrate. A complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the substrate. Efficient routing of these signals across the device requires formation of multilevel or multilayered schemes, such as, for example, single or dual damascene wiring structures. The wiring structure typically includes copper, Cu, since Cu based interconnects provide higher speed signal transmission between large numbers of transistors on a complex semiconductor chip as compared with aluminum, Al, based interconnects.
Within a typical interconnect structure, metal vias run perpendicular to the semiconductor substrate and metal lines run parallel to the semiconductor substrate. Further enhancement of the signal speed and reduction of signals in adjacent metal lines (known as “crosstalk”) are achieved in today's IC product chips by embedding the metal lines and metal vias (e.g., conductive features) in a dielectric material having a dielectric constant of less than 4.0.
In current interconnect structures, a layer of plasma vapor deposited (PVD) TaN and a PVD Cu seed layer are used as a Cu diffusion barrier and plating seed, respectively, for advanced interconnect applications. However, with decreasing critical dimension, it is expected that the PVD-based deposition techniques will run into conformality and coverage issues. These, in turn, will lead to fill issues at plating, such as center and edge voids, which cause reliability concerns and yield degradation.
One way around this problem is to reduce the overall thickness of PVD material, and utilize a single layer of liner material which serves as both the diffusion barrier and plating seed. Another way around the aforementioned issue is the use of chemical vapor deposition (CVD) or atomic layer deposition (ALD) which result in better step coverage and conformality as compared with conventional PVD techniques. CVD or ALD ruthenium, Ru, and iridium, Ir, have the potential of replacing current PVD based barrier/plating seed for advanced interconnect applications. See, for example, M. Lane et al., “Liner Materials for Direct Electrodeposition of Cu”, Appl. Phys. Letters, 83, n12, 2330 (2003) and M. Lane et al., “Interfacial Relationships in Microelectronic Devices”, Mat. Res. Soc. Symp. Proc., 766, 153 (2003).
The use of CVD or ALD Ru, Ir or other like noble metal is also advantages since Cu and other like metal conductors exhibit good adhesion to noble metals such as, for example, Ru. Moreover, a noble metal-Cu system is thermodynamically stable and has been shown to be substantially immiscible. Furthermore, noble metals such as Ru do not oxidize easily and have a fairly low bulk resistivity. The low resistivity of such noble metals is a necessary feature for it to enable direct electroplating of Cu.
Despite the above advantages that can be obtained utilizing noble metal liners, recent experimental results have revealed poor adhesion between the noble metal liner and the dielectric interface. It is likely that a noble metal, such as Ru, bonds weakly with C and O, and this may be a fundamental problem with deposition of a noble metal directly onto a dielectric surface. Because of the poor noble metal/dielectric adhesion issue, wafer peeling problems have been observed during Cu electroplating and chemical-mechanical polishing (CMP).
In addition to the above problem, prior art processes for fabricating interconnect structures typically use a photoresist and lithography to provide openings within the dielectric material. The patterned photoresist formed during the lithographic step is stripped by a plasma process which tends to damage the sidewalls of the dielectric material. The commonly employed post plasma strip wet clean in dilute hydrofluoric acid (HF) leads to the dissolution of the plasma damaged (i.e., modified dielectric material sidewalls). This in turn results in the increase in line width of the trench after etching; the extent of change is typically greater when more aggressive plasma strip processes are employed, or when more porous ultra low k dielectric materials are employed.
One has to account for this change by lithographically printing and etching smaller trench widths such that the change in line width due to the wet clean step can be accommodated. This becomes increasingly difficult when more porous and lower dielectric constant dielectric materials are used (e.g., a greater increase in line width after wet clean) and finer line widths for gigascale integration are desired.
Using milder plasma strip processes and gentler wet cleans are not always desirable as the efficacy of removal of residual patterned layers (such as, for example, via fills or photoresist) and reactive ion etching (RIE) process induced residues is compromised leading to higher contact resistance and lower product yield.
In view of the above, there is a need for providing an interconnect structure in which the adhesion problem and/or increased line width problem induced by plasma etching have been addressed.